This disclosure relates to semiconductor devices, such as image sensor semiconductor device packages (such as complementary metal-oxide-semiconductor (“CMOS”) sensors and charge-coupled device (“CCD”) sensors), and to various sensor semiconductor device packages (such as illuminance sensors and ultraviolet (“UV”) sensors), as well as semiconductor chip lamination packages (such as memory, and memory+logic), and to methods of manufacturing semiconductor devices.
A semiconductor device called a CSP (chip size package) includes through vias (through holes) formed from a rear surface of a semiconductor substrate, exposed pad electrodes formed on a surface of the semiconductor substrate, wirings formed from the exposed pad electrodes through the through vias, and external terminals provided on the rear surface of the semiconductor substrate. See, for example, Japanese Patent Application Laid-Open No. 2006-128171, which is incorporated by reference. In such a semiconductor device, the surface of the semiconductor substrate is normally covered with a passivation film (insulation layer). The passivation film is formed so as to cover the pad electrodes, and the passivation film is removed to form openings exposing a part of an electrode layer for carrying out electric property inspection or forming other electric connections.